1. Field of the Invention
The present invention relates generally to bus circuits of the precharge type, and more particularly, to improvement of a bus circuit of the precharge type used for transmitting data in a semiconductor integrated circuit such as a microprocessor.
2. Description of the Background Art
FIG. 4 is a schematic block diagram showing one example of a conventional bus circuit of the precharge type used for an integrated circuit device such as a microprocessor. In FIG. 4 , connected to a bus interconnection 1 are registers 11a, 11b, 11c and 11d each functioning as bus source and destination, and which registers as a whole constitute a register file 11 of the microprocessor. These registers are for temporarily storing the data for an operation in an ALU (not shown) or the like, and the data is transferred between these registers through the bus interconnection 1 when necessary. The bus interconnection 1 is connected to a power supply 3 through a P channel transistor 2.
Such a transfer operation of the data between the registers is performed by a microinstruction 5 stored in an instruction register 4 constituting a part of the microprocessor. More specifically, a bus destination register selecting instruction 5a in the microinstruction 5 is applied to one decoder 7 constituting a selection signal generating circuit 6, so that the decoder 7 generates signals SEL1a-SEL1d for selecting a register as a bus destination in response to the microinstruction and supplies the same to the registers 11a-11d respectively.
On the other hand, a bus source register selecting instruction 5b in the microinstruction 5 is applied to the other decoder 8 constituting the selection signal generating circuit 6, so that the decoder 8 generates signals SEL2a-SEL2d for selecting a register as a bus source in response to the microinstruction and supplies the same to the registers 11a-11d respectively.
A timing generating circuit 9 generates various timing signals T.sub.PC, T.sub.BS, T.sub.1 and T.sub.2 which will be describe later, and the T.sub.PC is supplied to a gate of the P channel transistor 2 and the T.sub.BS, T.sub.1 and T.sub.2 together are supplied in common to each of the registers.
FIG. 5 is a circuit diagram showing in detail the register file 11 shown in FIG. 4, which particularly shows circuit structures of the registers 11a and 11d while those of the registers 11b and 11c are not shown. Since the registers 11a and 11d have completely the same structure in FIG. 5, a description will be given to the structure of the register 11a, but not to that of register 11d.
The register 11a is mainly comprised of a destination latch 12a, a logic circuit 10a, a source latch 13a and a bus driver circuit 14a. The destination latch 12a is for receiving the data transferred from a source register through the bus interconnection 1 and an operation thereof is controlled by a logical product of the timing signal T.sub.1 from the timing generating circuit 9 and the signal SEL1a from the decoder 7. The source latch 13a is for holding the data to be transferred to the destination register through the bus interconnection 1 and an operation thereof is controlled by the timing signal T.sub.2 from the timing generating circuit 9. The bus driver circuit 14a is comprised of N channel transistors 15a and 16a connected in series between the bus interconnection 1 and a ground, wherein a logical product of the timing signal T.sub.BS from the timing generating circuit 9 and the signal SEL2a from the decoder 8 is applied to a gate of the transistor 15a and an output of the source latch 13a is applied to a gate device such as a gate, a memory, an ALU and a CPU.
FIG. 6 is a timing chart for explaining an operation of the bus circuit of the precharge type shown in FIGS. 4 and 5. Now, referring to FIGS. 4 through 6, a description will be given to an operation of a conventional bus circuit of the precharge type, for example, in case the data held in the register 11a is transferred to the register 11d.
First, the precharging P channel transistor 2 is turned on during a period the R.sub.PC (FIG. 6 (a)) generated from the timing generating circuit 9 is at the "L" (logical low) level, whereby current flows from the power supply 3 to the bus interconnection 1 through the transistor 2, so that a potential on the bus interconnection 1 attains the "H" (logical high) level. During this period, the T.sub.BS generated from the timing generating circuit 9 remains at the "L" level. Subsequently, when the T.sub.PC rises to the "H" level, the P channel transistor 2 is turned off but the T.sub.BS remains at the "L" level, and the N channel transistor 15a remains off. Accordingly, during the period the T.sub.BS is at the "L" level (precharge period), the potential on the bus interconnection 1 remains at the "H" level.
Now considering a case in which the data to be transferred is at the "H" level, a signal held in the latch 13a of the register 11a is at the "H" level. In addition, in this case, since the register 11a is selected as a source for the bus, the selection signal SEL2a supplied from the decoder 8 attains the "H" level (FIG. 6 (a)) . Accordingly, when the T.sub.PC rises to the "H" level followed by the T.sub.BS rising to the "H" level, the N channel transistor 15a forming the bus driver circuit 14a is turned on at that time. Since the output of the latch 13a is at the "H" level at that time as described above, the N channel transistor 16a is turned on, and at the same time as the turning on of the transistor 15a, the bus interconnection 1 is connected to the ground potential, so that the potential on the bus interconnection is lowered to the " L" level.
In addition, since the register 11d is selected as a bus destination, the selection signal SELld supplied from the decoder 7 attains the "H" level (FIG. 6 (f)). Accordingly, the latch 12d of the register 11d is operated in response to the timing signal T.sub.1 from the timing generating circuit 9, whereby the inversion data is taken to the latch 11d from the bus interconnection 1.
On the other hand, in case the data to be transferred is at the "L" level, the N channel transistor 16a is not turned on, and therefore no electric charge on the bus interconnection 1 is discharged, so that the potential thereon remains the "H" level. Accordingly, the inversion data is taken from the bus interconnection 1 to the latch 12d of the register 11d in response to the timing signal T.sub.1.
However, in the conventional bus circuit of the precharge type comprised of one bus interconnection as described above, if the number of registers as bus source and destination is increased, a length of the bus interconnection is increased, whereby the number of the transistors to be driven is also increased. Consequently, interconnection resistance and load capacitance of the bus are increased, resulting in the increase of the time for discharging electricity from the precharged bus. As a result, a data transferring operation in a microprocessor is delayed, thereby making it impossible to shorten a machine cycle. Therefore, a hierarchical structure of a bus interconnection is proposed comprising first and second buses each including only a single bus, which is disclosed in Japanese Patent Laying Open No. 63-26717. However, the delay in discharging the electricity from the bus can not be prevented completely by such a hierarchical structure in case that there is provided so many registers. In addition, with the hierarchical architecture shown in this reference, a decoding circuit of a microinstruction becomes complicated if the bus is simply divided into some portions and interconnections are provide for respective portions.